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| Integrated Circuit Systems, Inc. ICS9177 High Frequency System Clock Generator General Description The ICS9177 is a multiple output clock generator ideal for high speed processor system applications. A single highspeed internal VCO is utilized to derive up to four simultaneous clock output frequencies. This enables output clock skew matching and the minimization of clock jitter. The internal VCO operates up to 350 MHz providing edge skew matched output clocks. One differential PECL (Positive ECL) output pair provides a high speed processor clock. 12 TTL clock outputs are also provided for other system functions, such as bus clocks. Input selection pins are used to select the TTL output clock frequencies. For information about ICS9177 customization optics, please contact ICS. Features * * * * * * * * Provides output frequencies up to 175 Mhz Internal VCO is divided into four skew-matched output frequencies (Out A, B, C, D) External clock feedback provides input to output skew matching Differential PECL clock output pair provided for high speed output (Out A) 12 TTL clock outputs (for Out B, C, D) Single 5 volt power supply voltage Internal loop filters 52-pin QFP package Block Diagram Pin Configuration 52-Pin QFP ICS9177RevB060297P ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9177 Pin Description PIN PIN NUMNAME BER 1 GND 2 REFCLK 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FBCLK DSEL1# DSEL0# TESTEN TSTCLK NC VCC GND PCOUT1 PCOUT0 GND VCC PBOUT1 PBOUT0 VCC GND PAOUT1 PAOUT0 VCC GND RESETL BOUT1 BOUT0 VCC GND TYPE DESCRIPTION PIN NUMBER 28 29 30 31 32 33 34 35 36 37 38 39 PIN NAME COUT2 COUT1 VCC GND COUT0 DOUT0 GND NC AOUT1 AOUT0 NC GND ECL+5V (same as VCC) NC NC ANALOG +5V ANALOG +5V AGND PCSEL1 PCSEL0 PBSEL1 PBSEL0 PASEL1 PASEL0 VC INPUT INPUT INPUT INPUT INPUT INPUT Programmable clock Group A select Programmable clock Group B select Programmable clock Group C select OUTPUT ECL - 100 MHz, 75 MHz or 50 MHz based on DSEL(1:0) OUTPUT pins TYPE OUTPUT OUTPUT DESCRIPTION TTL - 25 MHz output clock INPUT INPUT INPUT INPUT INPUT INPUT from external oscillator external PLL Feedback path from one of the OutC outputs PLL divider mode control (Contains internal pull-up resistors) Test mode ENABLE pin External Test Clk TTL - 25 MHz output clock TTL - 12.5 MHz output clock OUTPUT TTL - Group 2 OUTPUT Programmable clock outputs 40 41 42 OUTPUT TTL - Group 1 OUTPUT Programmable clock outputs 43 44 45 OUTPUT TTL - Group 0 OUTPUT Programmable clock outputs 46 47 48 INPUT Low true divider reset pin OUTPUT TTL - 50 MHz output clock OUTPUT 49 50 51 52 *Internal pull-up resistor 2 ICS9177 Typical System Usage Example of System Block Diagram - Clocking Function Tables Table 1: Primary Function Table Typical System Usage REF IN (MHx) 25 25 33 25 DSEL1# DSEL0# 0 0 1 1 X 0 0 1 1 0 1 0 1 X 0 1 0 1 RSTL 1 1 1 1 0 1 1 1 1 TEST 0 0 0 0 X 1 1 1 1 f1 OUT A f/4 f/4 f/2 OUT B f/4 f/6 f/4 OUT C f/8 f/12 f/8 OUT D f/16 f/24 f/16 DESCRIPTION Mode 0 - 1/1 Mode 1 - 3/2 Mode 2 - 2/1 Mode 3 - A ll 1 Reset Mode Test Mode 0 Test Mode 1 Test Mode 2 Test Mode 3 200 MHz 300 Mhz 200/264 MHz X X TCLK TCLK TCLK TCLK 1 0 f/2 f/2 f/1 f/2 1 0 f/2 f/3 f/2 f/2 1 0 f/4 f/6 f/4 f/2 1 0 f/8 f/12 f/8 f/2 Table 2: CLOCK SELECT Blocks Function Table PxSEL 1 0 0 1 1 PxSEL 0 0 1 0 1 Function of CLOCK SELECT Blocks Both outputs at the same frequency as Out B. Both outputs at the same frequency as Out C. Both outputs at the same frequency as Out D. Both outputs disabled in the high state. Note: x=A, B, or C. (See Figure 1.) 3 ICS9177 Clock Output Timing Diagrams 1:1 frequency ratio - Mode 0 3:2 frequency ratio - Mode 1 2:1 frequency ratio - Mode 2 Note: The arrow indicates the point where the clock sequence starts to repeat. 4 ICS9177 Absolute Maximum Ratings Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND -.05V to VDD +.05V Ambient operating temperature . . . . . . . . . . . . . . . . 0C to +70C Storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Power Supply Specifications (Total Power consumption: approximately 750 mw) Table 3: DC Specifications Supply VDD I(typ) 150 mA I(max) 200 mA V(min) 4.75V V(typ) 5V V(max) 5.25V AC/DC Input Specification Table 4: AC Specification of Inputs Pin Type All Vih(min) 2V Vil(max) 0.8V tr 3 tf 3 Note: tr and tf are typical values for input AC/DC Characteristics Table 5: AC Specification type Out A.pecl Pins (CPUCLK) PARAMETER Output High Voltage 1 Output Low Voltage 1 Output High Current Output Low Current Rise Time 10-90% Fall Time 10-90% Duty cycle at 100 MHz 2, 3 SYMBOL Voh Vol Ioh Iol tr tf dcyc TEST CONDITIONS MIN 3.87 2.63 38.7 26.3 TYP MAX 4.67 3.19 46.7 31.9 1 1 55 UNITS volts volts ma ma ns ns % 45 Test Load Conditions: 100, 15 pF. Note 1: The pecl levels are standard 10 kHz positive ECL values as shown in the table above. Note 2: Pin skew and Duty cycle are measured at the signal swing mid-point. Note 3: The skew and duty cycle numbers reflect the recommended clock distribution method shown in Figure 2 5 ICS9177 Table 6: AC Specification type Out B.ttl Pins (50 MHz) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 10-90% Fall Time 10-90% Pin skew to other OutB.ttl signals 1 Duty cycle at 1.5V Delay from OutA.pecl signals Skew associated with above delay 3 2 SYMBOL Voh Vol Ioh Iol tr tf tsk dcyc tdly tdlyskw TEST CONDITIONS MIN 2.4 0 16 1 1 TYP 3.2 0.3 MAX 5 0.8 24 3 3 500 55 UNITS volts volts mA mA ns ns ps % ns ns 2 2 250 45 .2 .5 0.5 Test Load Conditions: 500, 15 pF. Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group. Note 2: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from the OutA.pecl signal at the signal swing mid-point to max output of the OutB.ttl signal's rising edge Table 7: AC Specification type Out C.ttl Pins (25 MHz) PARAMETER Output High Voltage Output Low Voltage Output High Current Output Low Current Rise Time 10-90% Fall Time 10-90% Pin skew to other OutC.ttl signals 1 Duty cycle at 1.5V Spread to OutB.ttl signals 2 SYMBOL Voh Vol Ioh Iol tr tf tsk dcyc tspb 45 TEST CONDITIONS MIN 2.4 0 16 1 1 TYP 3.2 0.3 MAX 5 0.8 24 3 3 500 55 500 UNITS volts volts mA mA ns ns ps % ps 2 2 250 Test Load Conditions: 500, 15 pF. Note 1: Pin skew is measured from the earliest rising edge of the group to the latest rising edge of the group. Note 2: Spread is the absolute difference between the rising edge of any OutC.ttl signal and the rising edge of any OutB.ttl signal 6 ICS9177 Table 8: AC Specification type Out D.ttl Pins (12.5 MHz) Output Output Output Output PARAMETER High Voltage Low Voltage High Current Low Current SYMBOL Voh Vol Ioh Iol tr tf tsk dcyc tdly tdlyskw 45 TEST CONDITIONS MIN 2.4 0 16 1 1 TYP 5 0.8 24 3 3 500 55 .5 1.3 2 2 250 MAX 3.2 0.3 UNITS volts volts mA mA ns ns ps % ns ns Rise Time 10-90% Fall Time 10-90% Pin skew to other OutD.ttl signals Duty cycle at 1.5V Delay from OutA.pecl signals Skew associated with above delay 2 1 Test Load Conditions: 500W, 15 pF. Note 1: Delay is the intrinsic delay between the TTL drivers switching and the PECL driver switching. This is measured from the OutA.pecl signal at the signal swing mid-point to max output of the OutD.ttl signal's rising edge 7 ICS9177 52-Pin QFP Package LEAD COUNT BODY THICKNESS FOOTPRINT (BODY+) DIMENSIONS TOLERANCE A MAX. A1 D D1 E E1 L e b ccc 44L 52L 64L 2.0 80L 3.20 100L 64L 80L 2.70 100L 2.45 0.25 13.20 10.0 13.20 10.0 0.70 0.80 17.20 14.00 17.20 14.00 0.88 1.00 0.35 0.10 0 - 7 1.00 0.80 0.65 0.30 17.20 14.00 23.20 20.00 0.88 1.00 0.35 3.40 0.25 MAX. 0.25 0.10 0.25 0.10 0.15/-0.10 BASIC +0.05 MAX 0.80 0.65 0.30 Ordering Information ICS9177-01CF52 Example: ICS XXXX-PPP M X#W Lead Count & Package Width Lead Count=1, 2 or 3 digits W=.3" SOIC or .6" DIP; None=Standard Width Package Type F=QFP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. 8 |
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